Testing of integrated circuit devices identifies devices that are defective and also provides information regarding the yield of or problems in the fabrication process. Preferably testing is performed early in the fabrication process to avoid wasted processing of defected parts and to identify process problems before a correctable problem affects multiple batches. Wafer probing in particular permits early electrical testing of integrated circuit devices before the devices are separated from a wafer. The devices identified as being defective or bad can then be discarded before being packaged. Further, corrections or adjustments to the fabrication process can be made without the additional delay that would result if devices were only tested after being packaged.
FIG. 1 illustrates conventional test equipment 100 for the testing of an integrated circuit device 112 fabricated on a wafer 110. Wafer 110 generally is a semiconductor wafer that includes multiple devices 112. For testing, a prober or other positioning system (not shown) moves wafer 110 or a test head 130 to align a test board 120 with the device 112 currently selected for testing. On test board 120 are pins 124 arranged to match the pattern of electrical terminals 114 on each device 112. When test board 120 is appropriately aligned with the selected device 112, pins 124 and terminals 114 are brought together to provide electrical connections between the selected device 112 and test board 120. Pins 124, test board 120, and test head 130 can then relay electrical signals between the selected device 112 and test electronics 140.
Test equipment 100 is generally designed to avoid or minimize damage to devices 112, particularly where pins 124 contact terminals 114. In FIG. 1, pins 124 are cantilevered to provide flexibility that limits the force that pins 124 apply to terminals 114. Some other similar test equipment designs use spring-loaded pins that similarly cushion or limit the force applied to devices 112 during testing.
A disadvantage of pins 124 being flexible is the ease with which pins 124 become misaligned. When one of pins 124 is bent during cleaning or use, for example, that pin 124 will often fail to make a good electrical contact with the target terminal 114, resulting in a failed test. Further, a difference in the thermal properties of wafer 110 and test board 120 or pins 124 limits the temperature range at which pins 124 will suitably match the pattern of terminals 114. Particularly, pins 124 are long relative to the size of device 112 and will proportionally change in length when the temperature changes.
Damage or abrasion that testing causes on terminals 114 can be a problem even when pins 124 are compliant, and such damage is particularly problematic when device 112 is designed for flip-chip packaging. FIG. 2 illustrates a flip-chip package 200 including a die 210 and an interconnect substrate 220. Die 210 contains a device 112 that has been separated from a wafer such as wafer 110 of FIG. 1. Flip-chip packaging attaches metal bumps, which form elevated electrical terminals 114 on device 112, to pads 224 on interconnect substrate 220. Interconnect substrate 220 then provides electrical connections between die 210 and external terminals 222.
Sharp test pins 124 that contact terminals 114 before the packaging process can leave gouges 216 in terminals 114, particularly when the contacted portion of terminals 114 are relatively soft metal such as solder. Gouges 216 can trap contaminants such as oxidation or soldering flux that weaken joints between terminals 114 and pads 214, resulting in a less dependable package.
Another potential problem in flip-chip packages arises from the non-uniformity of terminals 114. In particular, for a reliable attachment of terminals 114 to pads 214, the tops of terminals 114 and pads 214 should lie in a plane corresponding to the packaging substrate. FIG. 2 illustrates the problem of a terminal 114′ that fails to extend to or make a reliable connection with a corresponding pad 214. The formation process for terminals 114 would typically be the cause of non-uniform terminals 114, but pins 124 can abrade selected terminals 114 during testing and further disrupt planarity, making reliable packaging more difficult.